# WCH CH32V407 & CH32V467 RISC‑V Dual USB 2.0 High‑Speed Development Board

The AnalogLamb CH32V407/CH32V467 development board brings WCH’s most powerful Qingke® RISC‑V3V interconnect MCUs to your bench. Both chips run at **up to 200 MHz zero‑wait execution**, score **4.11 CoreMark/MHz**, and integrate **two independent USB 2.0 High‑Speed transceivers (480 Mbps)​** with on‑chip PHYs – no external PHY required.

💡 The CH32V467 variant adds **4 MB or 8 MB of on‑chip PSRAM**​ and supports DMA block transfers up to 800 MB/s, making it ideal for GUI, imaging, and edge‑AI workloads.

### Key Features

*   **Dual RISC‑V cores options**​ – Choose CH32V407 (512 KB zero‑wait Flash, 200 KB SRAM) or CH32V467 (adds 4/8 MB PSRAM)
    
*   **Two USB 2.0 HS ports @ 480 Mbps**​ – Each with built‑in PHY, freely switchable between Host and Device mode
    
*   **Built‑in 10/100M Ethernet MAC + PHY**​ – Auto‑MDIX and polarity auto‑adaptation, no external PHY chip needed
    
*   **RVV Vector Extension**​ – Accelerates DSP, FFT, image processing, and on‑device AI inference
    
*   **Rich analog suite**​ – 2 × 12‑bit ADCs, 2 × 12‑bit DACs, onboard OPA and high‑speed comparators
    
*   **High‑speed data interfaces**​ – DVP camera interface (up to 150 MHz), SDIO (4‑line 80 MHz / 8‑line 50 MHz), FSMC, and LTDC display controller
    
*   **Massive I/O expansion**​ – 10 × USART, 1 × I2C, 1 × I3C (12.5 MHz, in‑band interrupt), 3 × SPI, 2 × I²S, 1 × CAN 2.0B
    
*   **Ultra‑low power**​ – Standby current as low as **1.5 µA**
    
*   **Industrial temperature range**​ – −40 °C to +85 °C
    
*   **Total 24 channels of DMA**​ across two controllers for zero‑CPU‑load data movement
    

![](//cnres.appracle.com/48217e5f408d74dbee47d58882b29b7b.jpg align="center")

### Why Choose This Development Board?

| Pain Point | How CH32V407/CH32V467 Solves It |
| --- | --- |
| Need multiple USB devices (U‑disk, scanner, webcam) simultaneously | **Two independent USB 2.0 HS ports**, each with on‑chip PHY |
| Ethernet design too costly / complex | **Integrated 100M PHY**​ eliminates external chip, saving BOM cost and PCB area |
| DSP/AI on Cortex‑M4 is sluggish | **RVV vector extension**​ boosts parallel math, beating Cortex‑M4 per MHz |
| Large frame buffers require external SDRAM | \*\*8 MB PSRAM on‑chip (CH32V467)\*\*​ with 800 MB/s DMA throughput |
| Rich peripheral set for industrial control | 10 USARTs, I3C, CAN, dual ADC/DAC, OPA – everything on one chip |

* * *

### Typical Applications

1.  **Industrial IoT gateways**​ – Dual USB HS + Ethernet for multi‑protocol bridging
    
2.  **USB device emulation / protocol analyzers**​ – Host & Device modes on separate ports
    
3.  **Edge AI & DSP**​ – RVV‑accelerated audio/voice recognition and simple vision pipelines
    
4.  **Human‑machine interfaces (HMI)** – LTDC + PSRAM drives high‑res color TFT/LCD
    
5.  **Camera capture systems**​ – DVP interface streams sensor data straight into PSRAM via DMA
    
6.  **Motor control & power electronics**​ – Advanced timers with dead‑time, brake, complementary PWM
    

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### Technical Specifications Summary

| Item | CH32V407 | CH32V467 |
| --- | --- | --- |
| Core | Qingke RISC‑V3V, 200 MHz | Qingke RISC‑V3V, 200 MHz |
| Vector Extension | RVV supported | RVV supported |
| Flash | 512 KB zero‑wait + 480 KB | 512 KB zero‑wait + 480 KB |
| SRAM | 200 KB | 200 KB |
| On‑chip PSRAM | – | 4 MB / 8 MB |
| USB 2.0 | 2 × HS (480 Mbps) with PHY | 2 × HS (480 Mbps) with PHY |
| Ethernet | 10/100M MAC + PHY | 10/100M MAC + PHY |
| ADC / DAC | 2 × 12‑bit / 2 × 12‑bit | 2 × 12‑bit / 2 × 12‑bit |
| Operating voltage | 2.9 V – 3.6 V | 2.9 V – 3.6 V |
| Packages available | LQFP64 / QFN68 / LQFP100 | LQFP64 / QFN68 / LQFP100 |

*Source: WCH official CH32V407 datasheet.*

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### Development Ecosystem

*   **IDE:​** MounRiver Studio (MRS) – free, Eclipse‑based, fully integrated toolchain
    
*   **Debugger:** Supports single‑wire or dual‑wire debug mode
    
*   **Bootloader:​** USART / USB upgrade supported
    
*   **Community:** AnalogLamb’s Polos family boards start at just **$1.99**, making RISC‑V accessible to hobbyists and professionals alike
    

* * *

### Frequently Asked Questions (FAQ)

**Q1: What is the difference between CH32V407 and CH32V467?**

A: The CH32V467 adds 4 MB or 8 MB of on‑chip PSRAM while keeping the same peripheral set. If your application needs large buffers (GUI, image, AI tensors), choose CH32V467; otherwise CH32V407 offers the same dual USB HS, Ethernet, and RISC‑V core at lower cost.

**Q2: Can both USB ports work simultaneously as Host and Device?**

A: Yes. Each of the two USB 2.0 HS controllers has an independent built‑in PHY and can be configured as Host, Device, or OTG independently, so you can have one port acting as a USB device (e.g., CDC/VCP to PC) while the other acts as a Host (e.g., reading a U‑disk).

**Q3: Do I need an external PHY for Ethernet?**

A: No. The chip integrates a 10/100M Ethernet PHY on‑die, requiring only a few passive components. This dramatically reduces BOM cost and PCB layout complexity compared to designs that need an external PHY.

**Q4: Is this board suitable for running machine‑learning models?**

A: Absolutely. The RVV vector extension accelerates DSP and integer matrix operations, and the CH32V467’s 8 MB PSRAM provides ample space for model weights and activations. It is well‑suited for lightweight edge‑AI tasks such as keyword spotting, sensor fusion, and simple image classification.

**Q5: What development tools do I need?**

A: Download MounRiver Studio (free). Connect a WCH‑Link debugger (or any compatible RISC‑V debug probe) to the board’s debug header. The chip also supports bootloader upgrade via USART or USB, so you can flash firmware without a dedicated debugger.

## Buy It Now

You can buy it in [AnalogLamb](https://www.analoglamb.com/products/ch32v407-ch32v467-risc-v-dual-usb2-0-development-board) Website